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gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: july 2003 document no. 22209 - 0 preliminary data sheet GS9062 key features ? smpte 259m-c compliant scrambling and nrz nrzi encoding (with bypass) dvb-asi sync word inse rtion and 8b/1 0b encoding adjustable loop bandwidth user selectable additional processing features including: - anc data checksum, and line number calculation and insertion - trs and edh packet generation and insertion - illegal code remapping internal flywheel for no ise immune trs generation 20-bit / 10-bit cmos pa rallel input data bus 27mhz / 13.5mhz parallel digital input automatic standards detection and indication 1.8v core power supply and 3.3v charge pump power supply 3.3v digital i/o supply jtag test interface small footprint compatible with gs1560a, gs1561, gs1532, and gs9060 applications ? smpte 259m-c serial digital interfaces dvb-asi serial digital interfaces description the GS9062 is a dual-standard serializer with an integrated cable driver. when used in conjunction with the go1525 voltage controlled oscillator, a transmit solution can be realized for sd-sdi and dvb-asi applications. in addition to serializing the input, the GS9062 performs nrz-to-nrzi encoding and scrambling as per smpte 259m-c when operating in smpte mode. when operating in dvb-asi mode, the device will insert k28.5 sync characters and 8b/10b enc ode the data prior to serialization. parallel data inputs are provided for 10-bit multiplexed or 20-bit demultiplexed formats. an appropriate parallel clock input signal is also required. the integrated cable driver features an output mute on loss of parallel clock, high im pedance mode and adjustable signal swing. the GS9062 also includes a range of data processing functions including automatic standards detection and edh support. the device can also insert trs signals, re-map illegal code words and insert smpte 352m payload identifier packets. all processi ng features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming. hd-linx ? ii GS9062 sd-sdi and dvb-asi serializer
gennum corporation 22209 - 0 2 of 34 GS9062 GS9062 functional block diagram sdo sdo sdo_en/dis rset cp_cap h v f din[19:0] ioproc_en/dis dvb_asi i/o buffer & demux smpte 352m generation trs insertion, data blank, code- re-map and flywheel dvb-asi bypass reset_trst reset host interface / jtag test cs_tms sclk_tck sdin_tdi sdout_tdo jtag/host locked v co vco lf lb_cont vco_vcc vco_gnd 20bit/10bit dvb-asi sync word insert & 8b/10b encode edh generation & smpte scramble pclk blank detect_trs smpte_bypass phase detector, charge pump, vco control & power supply p -> s
gennum corporation 22209 - 0 3 of 34 GS9062 table of contents 1. pin out .................................................................................................................... ...................... 4 1.1 pin assignment............................................................................................................ .... 4 1.2 pin descriptions .......................................................................................................... .... 5 2. electrical characteristics ................................................................................................. ....... 11 2.1 absolute maxiumum ratings ........................................................................................ 11 2.2 dc electrical characteristics..................................................................................... 12 2.3 ac electrical characteristics..................................................................................... 13 2.4 input/output circuits .................................................................................................. 14 2.5 host interface maps .................................................................................................... 15 3. detailed description ....................................................................................................... ............ 18 3.1 functional overview .................................................................................................... 18 3.2 parallel data inputs.................................................................................................... 18 3.2.1 parallel input in smpte mode ............................................................................................ .......................18 3.2.2 parallel input in dvb-asi mode .......................................................................................... .......................18 3.2.3 parallel input in data-through mode..................................................................................... ..............19 3.2.4 parallel input clock (pclk) ............................................................................................. .........................19 3.3 smpte mode ................................................................................................................ ... 19 3.3.1 internal flywheel....................................................................................................... ..................................19 3.3.2 hvf timing signal extraction............................................................................................ ........................20 3.4 dvb-asi mode.............................................................................................................. .... 20 3.4.1 control signal inputs ................................................................................................... .............................20 3.5 data-through mode ...................................................................................................... 21 3.6 additional processing functions ............. .................................................................... 21 3.6.1 input data blank........................................................................................................ ....................................21 3.6.2 automatic video standard detection ...................................................................................... .............21 3.6.3 packet generation and insertion ......................................................................................... ..................23 3.7 parallel-to-serial conversion...................................................................................... 28 3.8 serial digital data pll .................................................................................................. 2 8 3.8.1 external vco............................................................................................................ .......................................28 3.8.2 lock detect output...................................................................................................... ................................28 3.9 serial digital output .................................................................................................... 2 8 3.9.1 output swing ............................................................................................................ ......................................29 3.9.2 serial digital output mute .............................................................................................. ..........................29 3.10 gspi host interface ..................................................................................................... 2 9 3.10.1 command word description............................................................................................... .....................29 3.10.2 data read and write timing ............................................................................................. ........................30 3.10.3 configuration and status registers ..................................................................................... .............30 3.11 jtag ..................................................................................................................... ........ 31 3.12 device power up.......................................................................................................... 31 3.13 device reset............................................................................................................. .... 31 4. application reference design ............................................................................................... ..... 32 4.1 typical application circuit ........................................................................................... 32 5. references & relevant standards ............................................................................................ 33 6. package & ordering information............................................................................................. .. 33 6.1 package dimensions ...................................................................................................... 33 6.2 ordering information................................................................................................... 34 7. revision history ........................................................................................................... ............... 34
gennum corporation 22209 - 0 4 of 34 GS9062 1. pin out 1.1 pin assignment dvb_asi ioproc_en/dis sdout_tdo sdin_tdi sclk_tck f v h din0 din1 io_gnd blank core_gnd core_vdd jtag/host cs_tms reset_trst vco_vcc cp_gnd vco_gnd lf vco locked cp_cap core_gnd core_vdd din19 din18 io_vdd pclk lb_cont vco detect_trs cp_vdd pd_vdd pd_gnd 20bit/10bit smpte_bypass rset din17 io_vdd din2 din3 din4 din5 din6 din7 din8 din9 io_gnd io_vdd din10 din11 din12 din13 din14 din15 din16 io_gnd 1 80 nc 2 3 4 5 6 7 79 78 77 76 75 74 73 8 9 10 11 12 13 14 72 71 70 69 68 67 66 65 64 63 62 61 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 nc nc cd_vdd sdo sdo cd_gnd sdo_en/dis nc nc nc nc nc nc nc nc nc nc rsv nc nc 9062
gennum corporation 22209 - 0 5 of 34 GS9062 1.2 pin descriptions pin number name timing type description 1 cp_vdd - power power supply connection for the charge pump. connect to +3.3v dc analog. 2 pd_gnd - power ground connection for the phase detector. connect to analog gnd. 3 pd_vdd - power power supply connection for the phase detector. connect to +1.8v dc analog. 4, 6 - 8, 10 - 11, 14 - 17, 31, 70 - 71 nc - - no connect. 5 rsv - - reserved ? connect to analog ground. 9 dvb_asi non synchronous input control signal input signal levels are lvcmos/lvttl compatible. when set high in conjunction with smpte_bypass = low, the device will be configured to operate in dvb-asi mode. when set low, the device will not support the encoding of received dvb- asi data. 12 20bit/10bit non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select the input data bus width in smpte or data-through modes. this signal is ignored in dvb-asi mode. when set high, the parallel input will be 20-bit demultiplexed data. when set low, the parallel input will be 10-bit multiplexed data. 13 ioproc_en/dis non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable i/o processing features. when set high, the following i/o processing features of the device are enabled: edh packet generation and insertion smpte 352m packet generation and insertion anc data checksum calculation and insertion trs generation and insertion illegal code remapping to enable a subset of these features, keep ioproc_en/dis high and disable the individual feature(s) in the ioproc_disable register accesible via the host interface. when set low, the i/o processing f eatures of the device are disabled, regardless of whether the features are enabled in the ioproc_disable register. 18 smpte_bypass non synchronous input control signal input signal levels are lvcmos/lvttl compatible. when set high in conjunction with dvb_asi = low, the device will be configured to operate in smpte mode. all i/o processing features may be enabled in this mode. when set low, the device will not support the scrambling or encoding of received smpte data. no i/o processing features will be available.
gennum corporation 22209 - 0 6 of 34 GS9062 19 rset analog input used to set the serial digital output signal amplitude. connect to cd_vdd through 281 ? +/- 1% for 800mv p-p single-ended output swing. 20 cd_vdd - power power supply connection for t he serial digital cable driver. connect to +1.8v dc analog. 21 sdo_en/dis non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable the serial digital output stage. when set low, the serial digital output signals sdo and sdo are disabled and become high impedance. when set high, the serial digital output signals sdo and sdo are enabled. 22 cd_gnd - power ground connection for the serial digital cable driver. connect to analog gnd. 23, 24 sdo, sdo analog output serial digital output signal operating at 270mb/s. the slew rate of these outputs is aut omatically controlled to meet smpte 259m specifications. 25 reset_trst non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to reset the internal operating conditions to default settings and to reset the jtag test sequence. host mode (jtag/host = low) when asserted low, all functional blocks will be set to default conditions and all input and output signals become high impedance, including the serial digital outputs sdo and sdo. must be set high for normal device operation. jtag test mode (jtag/host = high) when asserted low, all functional blocks will be set to default and the jtag test sequence will be held in reset. when set high, normal operation of the jtag test sequence resumes. 26 jtag/host non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select jtag test mode or host interface mode. when set high, cs _tms, sdout_tdo, sdi_tdi and sclk_tck are configured for jtag boundary scan testing. when set low, cs _tms, sdout_tdo, sdi_tdi and sclk_tck are configured as gspi pins for normal host interface operation. 27 cs _tms synchronous with sclk_tck input control signal input signal levels are lvcmos/lvttl compatible. chip select / test mode select host mode (jtag/host = low) cs _tms operates as the host interface chip select, cs , and is active low. jtag test mode (jtag/host = high) cs _tms operates as the jtag test mo de select, tms, and is active high. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 22209 - 0 7 of 34 GS9062 28 sdout_tdo synchronous with sclk_tck output control signal output signal levels are lvcmos/lvttl compatible. serial data output / test data output host mode (jtag/host = low) sdout_tdo operates as the host interf ace serial output, sdout, used to read status and configuration informati on from the internal registers of the device. jtag test mode (jtag/host = high) sdout_tdo operates as the jtag test data output, tdo. 29 sdin_tdi synchronous with sclk_tck input control signal input signal levels are lvcmos/lvttl compatible. serial data in / test data input host mode (jtag/host = low) sdin_tdi operates as the host interface serial input, sdin, used to write address and configuration information to the internal registers of the device. jtag test mode (jtag/host = high) sdin_tdi operates as the jtag test data input, tdi. 30 sclk_tck non synchronous input control signal input signal levels are lvcmos/lvttl compatible. serial data clock / test clock. host mode (jtag/host = low) sclk_tck operates as the host interface burst clock, sclk. command and data read/write words are clocke d into the device synchronously with this clock. jtag test mode (jtag/host = high) sclk_tck operates as the jtag test clock, tck. 32 blank synchronous with pclk input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable input data blanking. when set low, the luma and chroma input data is set to the appropriate blanking levels. horizontal and vertical ancillary spaces will also be set to blanking levels. when set high, the luma and chroma input data pass through the device unaltered. 33, 68 core_gnd - power ground connection for the di gital core logic. connect to digital gnd. 34 f synchronous with pclk input control signal input signal levels are lvcmos/lvttl compatible. used to indicate the odd / even field of the video signal when detect_trs is set low. the device will set the f bit in all outgoing trs signals for the entire period that the f input signal is high (ioproc_en/dis must also be high). the f signal should be set high for the entire period of field 2 and should be set low for all lines in field 1 and for all lines in progressive scan systems. the f signal is ignored when detect_trs = high. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 22209 - 0 8 of 34 GS9062 35 v synchronous with pclk input control signal input signal levels are lvcmos/lvttl compatible. used to indicate the portion of the video field / frame that is used for vertical blanking when detect_trs is set low. the device will set the v bit in all outgoing trs signals for the entire period that the v input signal is high (ioproc_en/dis must also be high). the v signal should be set high for the entire vertical blanking period and should be set low for all lines outside of the vertical blanking interval. the v signal is ignored when detect_trs = high. 36 h synchronous with pclk input control signal input signal levels are lvcmos/lvttl compatible. used to indicate the portion of the video line containing active video data when detect_trs is set low. the device will set the h bit in all outgoing trs signals for the entire period that the h input signal is high (ioproc_en/dis must also be high). h signal timing is configurable via the h_config bit of the ioproc_disable register, accessible via the host interface. active line blanking (h_config = 0 h ) the h signal should be set high for the entire horizontal blanking period, including the eav and sav trs word s, and low otherwise. this is the default setting. trs based blanking (h_config = 1 h ) the h signal should be set high for the entire horizontal blanking period as indicated by the h bit in the received trs id words, and low otherwise. 37, 64 core_vdd - power power supply connection for the digital core logic. connect to +1.8v dc digital. 38, 39, 42?48, 50 din[0:9] synchronous with pclk input parallel data bus signal levels are lvcmos/lvttl compatible. din9 is the msb and din0 is the lsb. 20-bit mode 20bit/10bit = high chroma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low high impedance in dvb-asi mode smpte_bypass = low dvb_asi = high 10-bit mode 20bit/10bit = low high impedance in all modes. 40, 49, 60 io_gnd - power ground connection for digi tal i/o buffers. connect to digital gnd. 41, 53, 61 io_vdd - power power supply connection for digital i/o buffers. connect to +3.3v dc digital. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 22209 - 0 9 of 34 GS9062 51, 52, 54?59, 62, 63 din[10:19] synchronous with pclk input parallel data bus signal levels are lvcmos/lvttl compatible. din19 is the msb and din10 is the lsb. 20-bit mode 20bit/10bit = high luma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low dvb-asi data input in dvb-asi modesmpte_bypass = low dvb_asi = high 10-bit mode 20bit/10bit = low multiplexed luma and chroma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data through mode smpte_bypass = low dvb_asi = low dvb-asi data input in dvb-asi mode smpte_bypass = low dvb_asi = high 67 detect_trs non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select the timing mode of the device. when set high, the device will lock t he internal flywheel to the embedded trs timing signals in the parallel input data. when set low, the device will lock the internal flywheel to the externally supplied h, v, and f input signals. 69 pclk - input parallel data bus clock signal levels are lvcmos/lvttl compatible. sd 20-bit mode pclk = 13.5mhz sd 10-bit mode pclk = 27mhz 72 locked synchronous with pclk output status signal output signal levels are lvcmos / lvttl compatible. the locked signal will be high whenever the device has correctly received and locked to smpte compliant data in smpte mode or dvb- asi compliant data in dvb-asi mode, or when the device has achieved lock in data-through mode. it will be low otherwise. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 22209 - 0 10 of 34 GS9062 73, 74 vco, vco analog input differential inputs for the external vco reference signal. for single ended devices such as the go1525, vco should be ac coupled to vco_gnd. 75 vco_gnd - output power ground reference for the external voltage controlled oscillator. connect to pins 2, 4, 6, and 8 of the go1525. this pin is an output. should be isolated from all other grounds. 76 vco_vcc - output power power supply for the external voltag e controlled oscillator. connect to pin 5 of the go1525. this pin is an output. should be isolated from all other power supplies. 77 lf analog output control voltage to external vo ltage controlled oscillator. nominally +1.25v dc. 78 cp_cap analog input pll lock time constant capacitor connection. normally connected to vco_gnd through 2.2nf. 79 lb_cont analog input control voltage to set the loop bandwidth of the integrated reclocker. normally connected to vco_vcc through 15k ? . 80 cp_gnd - power ground connection for the charge pump. connect to analog gnd. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 22209 - 0 11 of 34 GS9062 2. electrical characteristics figure 1 reflow solder profile 2.1 absolute maxiumum ratings parameter value/units supply voltage core -0.3v to +2.1v supply voltage i/o -0.3v to +4.6v input voltage range (any input) -2.0v to + 5.25v ambient operating temperature -20c < t a < 85c storage temperature -40c < t stg < 125c lead temperature (soldering, 10 sec) 230c note: see reflow solder profile 25?c 100?c 150?c 183?c 230?c 220?c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3?c/sec max 6?c/sec max
gennum corporation 22209 - 0 12 of 34 GS9062 2.2 dc electrical characteristics t a = 0c to 70c, unless otherwise specified. parameter symbol conditions min typ max units test level notes system operation temperature range t a 0-70c- 1 function termperature range -25 - 85 c - 2 digital core supply voltage core_vdd 1.65 1.8 1.95 v 1 1 digital i/o supply voltage io_vdd 3.0 3.3 3.6 v charge pump supply voltage cp_vdd 3.0 3.3 3.6 v phase detector supply voltage pd_vdd 1.65 1.8 1.95 v input buffer supply voltage buff_vdd 1.65 1.8 1.95 v cable driver supply voltage cd_vdd 1.71 1.8 1.89 v external vco supply voltage output vco_vcc 2.25 2.50 2.75 v 1 - +1.8v supply current i 1v8 - - 245 ma 7 5 +3.3v supply current i 3v3 --45ma7 - total device power p d - - 590 mw 7 5 esd protection on all pins - 1 - - kv - 3 digital i/o input logic low v il -- 0.8v1 - input logic high v ih 2.1 - - v 1 - output logic low v ol -0.20.4v 1 - output logic high v oh io_vdd - 0.4 -- v 1 - input rset voltage v rset rset=281 ? 0.54 0.6 0.66 v 1 4 output output common mode voltage v cmout 75 ? load, rset=281 ? 0.8 1.0 1.2 v 1 - test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing desi gn/characterization data of similar product. 9. indirect test. notes 1. all dc and ac electrical pa rameters within specification. 2. guaranteed functional. 3. mil std 883 esd protection will be applied to all pins on the device. 4. set by the value of the rset resistor. 5. sdo outputs enabled.
gennum corporation 22209 - 0 13 of 34 GS9062 2.3 ac electrical characteristics t a = 0c to 70c, unless otherwise shown parameter symbol conditions min typ max units test level notes system device latency smpte and data-through modes -21-pclk6- dvb-asi mode - 11 - reset pulse width t reset 1--ms73 parallel input parallel clock frequency f pclk 13.5 - 27.0 mhz 1 - parallel clock duty cycle dc pclk 40 50 60 % 1 - input data setup time t oh 1.5 - - ns 1 1 input data hold time t od 1.5 - - ns 1 1 serial digital output serial output data rate dr sdo -270-mb/s1 - serial output swing ? v sdd rset = 281 ? 75 ? load -800-mvp-p1 - serial output risetime 20% ~ 80% tr sdo orl compensation using recommended circuit 400 550 1500 ps 1 - serial output fall time 20% ~ 80% tf sdo orl compensation using recommended circuit 400 550 1500 ps 1 - serial output intrinsic jitter t ij pseudorandom and pathological signal -270350ps1 - serial output duty cycle distortion dcd sdo -20-ps12 gspi gspi input clock frequency f sclk --6.6mhz1- gspi input clock duty cycle dc sclk 40 50 60 % 3 - gspi input data setup time 0 - - ns 3 - gspi input data hold time - - 1.43 ns 3 - gspi output data hold time 2.10 - - ns 3 - gspi output data delay time - - 7.27 ns 3 - test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product. 9. indirect test. notes 1. with 15pf load. 2. serial duty cycle distorti on is defined here to be the difference between the width of a ?1? bit, and the width of a ?0? bit. 3. see section 3.12, figure 18.
gennum corporation 22209 - 0 14 of 34 GS9062 2.4 input/output circuits all resistors in ohms, all capacitors in farads, unless otherwise shown. figure 2 serial digital output figure 3 vco control output & pll lock time capacitor figure 4 pclk input figure 5 vco input figure 6 pll loop bandwidth control sdo sdo 300 cp_cap lf vdd 42k 63k pclk vdd 25 25 vco vco 1.5k 5k 800mv 8k lb_cont
gennum corporation 22209 - 0 15 of 34 GS9062 2.5 host interface maps register name address 15 14 13 12 11 10 9 8 7 6 5 43 210 line_352m_f2 1ch not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 line_352m_f1 1bh not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 1ah ff_line_end_f1 19h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f1 18h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_end_f0 17h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f0 16h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f1 15h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f1 14h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f0 13h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f0 12h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 raster_structure4 11h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 raster_structure3 10h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 raster_structure2 0fh not used not used not used not used b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 raster_structure1 0eh not used not used not used not used b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0dh 0ch video_format_b 0bh vf4-b7 vf4-b6 vf4-b5 vf4 -b4 vf4-b3 vf4-b2 vf4-b1 vf4-b0 vf3-b7 vf3-b6 vf3-b5 vf3-b4 vf3-b3 vf3-b2 vf3-b1 vf3-b0 video_format_a 0ah vf2-b7 vf2-b6 vf2-b5 vf2 -b4 vf2-b3 vf2-b2 vf2-b1 vf2-b0 vf1-b7 vf1-b6 vf1-b5 vf1-b4 vf1-b3 vf1-b2 vf1-b1 vf1-b0 09h 08h 07h 06h 05h video_standard 04h not used vds-b4 vds-b3 vds-b2 vds-b1 vds-b0 int_prog std_ lock not used not used not used not used not used not used not used not used 03h edh_flag 02h not used anc-ues anc-ida anc-idh anc-eda anc-edh ff-ues ff-i da ff-idh ff-eda ff-edh ap-ues ap-ida ap-idh ap-eda ap-edh 01h ioproc_disable 00h not used not used not used not used not used not used not used h_config not used 352m_ins illegal_ remap edh_crc _ins anc_ csum_ins not used not used trs_ins
gennum corporation 22209 - 0 16 of 34 GS9062 2.5.1 host interface map (read only registers) register nameaddress1514131211109876543210 1ch 1bh 1ah 19h 18h 17h 16h 15h 14h 13h 12h raster_structure4 11h b10b9b8b7b6b5b4b3b2b1b0 raster_structure3 10h b10b9b8b7b6b5b4b3b2b1b0 raster_structure2 0fh b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 raster_structure1 0eh b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0dh 0ch 0bh 0ah 09h 08h 07h 06h 05h video_standard 04h vds-b4 vds-b3 vds-b2 vds-b1 vds-b0 int_prog std_ lock 03h 02h 01h 00h
gennum corporation 22209 - 0 17 of 34 GS9062 2.5.2 host interface map (r/w configurable registers) register nameaddress1514131211109876543210 line_352m_f2 1ch b10b9b8b7b6b5b4b3b2b1b0 line_352m_f1 1bh b10b9b8b7b6b5b4b3b2b1b0 1ah ff_line_end_f1 19h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f1 18h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_end_f0 17h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f0 16h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f1 15h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f1 14h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f0 13h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f0 12h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 11h 10h 0fh 0eh 0dh 0ch video_format_b 0bh vf4-b7 vf4-b6 vf4-b5 vf4-b4 vf4-b3 vf4-b2 vf4- b1 vf4-b0 vf3-b7 vf3-b6 vf3-b5 vf3-b4 vf3-b3 vf3-b2 vf3-b1 vf3-b0 video_format_a 0ah vf2-b7 vf2-b6 vf2-b5 vf2-b4 vf2-b3 vf2-b2 vf2- b1 vf2-b0 vf1-b7 vf1-b6 vf1-b5 vf1-b4 vf1-b3 vf1-b2 vf1-b1 vf1-b0 09h 08h 07h 06h 05h 04h 03h edh_flag 02h anc-ues anc-ida anc-idh anc-eda anc-edh ff-ues ff-ida ff -idh ff-eda ff-edh ap-ues ap-ida ap-idh ap-eda ap-edh 01h ioproc_disable 00h h_config 352m_ins illegal_ remap edh_crc _ins anc_ csum_ins trs_ins
gennum corporation 22209 - 0 18 of 34 GS9062 3. detailed description 3.1 functional overview the GS9062 is a dual-standard serializer with an integrated cable driver. when used in conjunction with the external go1525 voltage controlled oscillator, a transmit solution at 270mb/s is realized. the device has three different modes of operation which must be set by the application layer through external device pins. when smpte mode is enabled, the device will accept 10- bit multiplexed or 20-bit demultiplexed smpte compliant data. the device?s additional processing features are also enabled in this mode. in dvb-asi mode, the GS9062 will accept an 8-bit parallel dvb-asi compliant transport stream on its upper input bus. the serial output data stream will be 8b/10b encoded and stuffed. the GS9062?s third mode allows for the serializing of data not conforming to smpt e or dvb-asi streams. the provided serial digital outputs feature a high impedance mode, output mute on loss of parallel clock and adjustable signal swing. in the digital signal pro cessing core, several data processing functions are implemented including smpte 352m and edh data packet generation and insertion, and automatic video standards dete ction. these features are all enabled by default, but may be individually disabled via internal registers accessible through the gspi host interface. finally, the GS9062 contains a jtag interface for boundary scan test implementations. 3.2 parallel data inputs data inputs enter the device on the rising edge of pclk as shown in figure 7. the input data format is defined by the setting of the external smpte_bypass and dvb_asi pins and may be presented in 10-bit or 20-bit format. the input data bus width is controlled independently from the internal data bus width by the 20bit/10bit input pin. figure 7 pclk to data timing 3.2.1 parallel input in smpte mode when the device is operating in smpte mode, (see section 3.3), data may be presented to the input bus in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit input pin. in 20-bit mode, (20bit/10bit = high), the input data format should be word aligned, demultiplexed luma and chroma data. luma words should be pr esented to din[19:10] while chroma words should occupy din[9:0]. in 10-bit mode, (20bit/10bit = low), the input data format should be word aligned, multiplexed luma and chroma data. the data should be pres ented to din[19:10]. din[9:0] will be high impedance in this mode. 3.2.2 parallel input in dvb-asi mode when operating in dvb-asi mode, (see section 3.4), the GS9062 automatically configures the input port for 10-bit operation regardless of the setting of the 20bit/10bit pin. the device will accept 8-bit data words on din[17:10] such that din17 = hin is the most significant bit of the encoded transport stream data and din10 = ain is the least significant bit. in addition, din19 and din18 will be configured as the dvb-asi control signals inss yncin and kin respectively. see section 3.4 for a descript ion of these dvb-asi specific input signals. din[9:0] will be high im pedance when the GS9062 is operating in dvb-asi mode. pclk din[19:0] data control signal input t is t ih
gennum corporation 22209 - 0 19 of 34 GS9062 3.2.3 parallel input in data-through mode when operating in data-throu gh mode, (see section 3.5), the GS9062 passes data presented to the parallel input bus to the serial output without performing any encoding or scrambling. the input data bus width accepted by the device in this mode is controlled by th e setting of the 20bit/10bit pin. 3.2.4 parallel input clock (pclk) the frequency of the pclk input signal required by the GS9062 is determined by the input data format. table 1 below lists the possible inpu t signal formats and their corresponding parallel clock ra tes. note that dvb-asi input will always be in 10-bit format, regardless of the setting of the 20bit/10bit pin. 3.3 smpte mode the GS9062 is said to be in smpte mode when the smpte_bypass pin is set high and the dvb_asi pin is set low. in this mode, the parallel da ta will be scrambled according to smpte 259m, and nrz-to-nrzi encoded prior to serialization. 3.3.1 internal flywheel the GS9062 has an internal flywheel which is used in the generation of internal / exte rnal timing signals, and in automatic video standards dete ction. it is operational in smpte mode only. the flywheel consists of a number of counters and comparators operating at video pixel and video line rates. these counters maintain information about the total line length, active line length, total number of lines per field / frame and total active lines per field / frame for the received video standard. when detect_trs is low, the flywheel will be locked to the externally supplied h, v, and f timing signals. when detect_trs is high, the flywheel will be locked to the embedded trs signals in the parallel input data. both 8-bit and 10-bit trs code words will be identified by the device. the flywheel 'learns' the video standard by timing the horizontal and vertical reference information supplied a the h, v, and f input pins, or contained in the trs id words of the received video data. full synchronization of the flywheel to the received video standa rd therefore requires one complete video frame. once synchronization has been achieved, the flywheel will continue to monitor the receiv ed trs timing or the supplied h, v, and f timing information to maintain synchronization. table 1 parallel data input format input data format control signals dout [19:10] dout [9:0] pclk 20bit/10bit smpte_bypass dvb_asi smpte mode 20bit demultiplexed high high low luma chroma 13.5mhz 10bit multiplexed low luma / chroma high impedance 27mhz dvb-asi mode 10bit dvb-asi high low high dvb-asi data high impedance 27mhz low data-through mode 20bit demultiplexed high low low data data 13.5mhz 10bit multiplexed low data high impedance 27mhz
gennum corporation 22209 - 0 20 of 34 GS9062 3.3.2 hvf timing signal extraction as discussed above, the GS9062's internal flywheel may be locked to externally provided h, v, and f signals when detect_trs is set low by the application layer. the h signal timing should also be configured via the h_config bit of the internal ioproc_disable register as either active line based blanking or trs based blanking, (see section 3.6.3). active line based blanking is enabled when the h_config bit is set low. in this mode, the h input should be high for the entire horizontal blanking period, including the eav and sav trs words. this is the default h timing assumed by the device. when h_config is set high, trs based blanking is enabled. in this case, the h input should be set high for the entire horizontal blanking period as indicated by the h bit in the associated trs words. the timing of these signals is shown in figure 8. figure 8 h, v, f timing 3.4 dvb-asi mode the GS9062 is said to be in dvb-asi mode when the smpte_bypass pin is set low and the dvb_asi pin is set high. in this mode, all smpte processing functions are disabled, and the 8-bit transport stream data will be 8b/10b encoded prior to serialization. 3.4.1 control signal inputs in dvb-asi mode, the din19 and din18 pins will be configured as dvb-asi contro l signals inssyncin and kin respectively. when inssyncin is set high, the device will insert k28.5 sync characters into the data stream. this function is used to assist system implementa tions where the GS9062 may be preceded by an external data fifo. parallel dvb-asi data may be clocked into the fifo at some rate less than 27mhz. the inssyncin input may then be connected to the fifo empty signal, thus providing a means of padding up the data transmission ra te to 27mhz. see figure 9. note: 8b/10b encoding will take place after k28.5 sync character insertion. kin should be set high whenever the parallel data input is to be interpreted as any special character defined by the dvb-asi standard (including the k28.5 sync character). this pin should be set low when the input is to be interpreted as data. note: when operating in dvb-asi mode, din[9:0] become high impedance. h:v:f timing ? 20-bit input mode pclk chroma data out luma data out h 000 3ff xyz (eav) 000 v f 000 3ff xyz (sav) 000 h:v:f timing ? 10-bit input mode multiplexed y/cr/cb data out pclk h v f xyz (eav) 000 000 3ff xyz (sav) 000 000 3ff h signal timing: h_config = low h_config = high
gennum corporation 22209 - 0 21 of 34 GS9062 figure 9 dvb-asi fifo implementation using the GS9062 3.5 data-through mode the GS9062 may be configured by the application layer to operate as a simple parallel-to-serial converter. in this mode, the device presents data to the output buffer without performing any scrambling or encoding. data-through mode is enabled only when both the smpte_bypass and dvb_asi pins are set low. 3.6 additional processing functions the GS9062 contains an additional data processing block which is available in smpte mode only, (see section 3.3). 3.6.1 input data blank the video input data may be 'blanked' by the GS9062. in this mode, all input video data except trs words are set to the appropriate blanking levels by the device. both the horizontal and vertical ancillary data spaces will also be set to blanking levels. this function is enabled by setting the blank pin low. 3.6.2 automatic video standard detection the GS9062 can detect the input video standard by using the timing parameters extrac ted from the received trs id words or supplied h, v, and f timing signals (see section 3.3.1). this information is presented to the host interface via the video_standard register (table 2). total samples per line, active samples per line, total lines per field/frame and active lines per field/frame are also calculated and presented to the host interface via the raster_structure registers (table 3). these line and sample count registers are updated once per frame at the end of line 12. this is in addition to the information contained in the video_standard register. after device reset, the four raster_structure registers default to zero. 8 8 ain ~ hin pclk = 27mhz inssyncin sdo clk_in clk_out fifo sdo write_clk <27mhz fe ts kin GS9062 kin read clk =27mhz table 2 host interface description for video standard register register name bit name description r/w default video_standard address: 04h 15 not used 14-10 vd_std[4:0] video data standard (see table 4) r 0 9 not used 8 std_lock standard lock: set high when flywheel has achieved full synchronization. r0 7-0 not used
gennum corporation 22209 - 0 22 of 34 GS9062 3.6.2.1 video standard indication the video standard codes reported in the vd_std[4:0] bits of the video_standard regi ster represent the smpte standards as shown in table 4. in addition to the 5-bit video standard code word, the video_standard register also contains an additional status bit. the std_lock bit will be set high whenever the flywheel has achieved full synchronization. the vd_std[4:0] and std_lock bits of the video_standard register will default to zero after device reset. these bits will also default to zero if the smpte_bypass pin is asserted low or if the locked output is low. table 3 host interface description for raster structure registers register name bit name description r/w default raster_structure1 address: 0eh 15-12 not used 11-0 raster_structure_1[11:0] words per active line r 0 raster_structure2 address: 0fh 15-12 not used 11-0 raster_structure_2[11:0] words per total line. r 0 raster_structure3 address: 10h 15-11 not used 10-0 raster_structure_3[10:0] total lines per frame r 0 raster_structure4 address: 11h 15-11 not used 10-0 raster_structure_4[10:0] active lines per field r 0 table 4 supported video standards vd_std[4:0] smpte standard video format length of hanc length of active video total samples smpte352m lines 16h 125m 1440x487/60 (2:1) (or dual link progressive) 268 1440 1716 3, 276 17h 1440x507/60 (2:1) 268 1440 1716 3, 276 19h 525-line 487 generic - - 1716 3, 276 1bh 525-line 507 generic - - 1716 3, 276 18h itu-r bt.656 1440x576/50 (2:1) (or dual link progressive) 280 1440 1728 9, 322 1ah 625-line generic (em) - - 1728 9, 322 1eh unknown sd - - - - - 00h-15h, 1ch, 1fh reserved
gennum corporation 22209 - 0 23 of 34 GS9062 3.6.3 packet generation and insertion in addition to input data blanking and automatic video standards detection, the GS9062 may also calculate, assemble and insert into the data stream various types of ancillary data packets and trs id words. these features are only available when the device is set to operated in smpte mode and the ioproc_en/dis pin is set high. individual insertion features may be enabled or disabled via the ioproc_disable register (table 5). all of the ioproc_disable register bits default to '0' after device reset, enabling all of the processing features. to disable any individual error correction feature, the host interface must set the corresponding bit high in this register. table 5 host interface description for internal processing disable register register name bit name description r/w default ioproc_disable address: 00h 15-9 not used 8 h_config horizontal sync timing input configuration. set low when the h input timing is based on active line blanking (default). set high when the h input timing is based on the h bit of the trs words. see figure 8. r/w 0 7not used 6 352m_ins smpte352m packet insertion. the ioproc_en/dis pin and smpte_bypass pin must also be set high. set high to disable. r/w 0 5 illegal_remap illegal code remapping. detection and correction of illegal code words within the active picture area (ap). the ioproc_en/dis pin and smpte_bypass pin must also be set high. set high to disable. r/w 0 4 edh_crc_ins error detection & handling (edh) cyclical redundancy check (crc) error correction. the ioproc_en/dis pin and smpte_bypass pin must also be set high. set high to disable. r/w 0 3 anc_csum_ins ancillary data checksum insertion. the ioproc_en/dis pin and smpte_bypass pin must also be set high. set high to disable. r/w 0 2-1 not used 0 trs_ins timing reference signal insertion. occurs only when ioproc_en/dis is high and smpte_bypass is high. set high to disable. r/w 0
gennum corporation 22209 - 0 24 of 34 GS9062 3.6.3.1 smpte 352m payload identifier insertion the GS9062 can generate and insert smpte 352m payload identifier ancillary data packets into the data stream, based on information programmed into the host interface. when this feature is enabled, the device will automatically generate the ancillary data preambles, (did, sdid, dbn, dc), and calculate the checks um. the smpte 352m packet will be inserted into the data stream according to the line number and sample position rules defined in the standard. where an alternate insertion line is required, the host interface may program the li ne_352m registers (table 6) with the appropriate line numbers. the insertion process will only take place if one or more of the four video_format regi sters (table 7) have been programmed with non-zero values. in addition, the GS9062 requires the 352m_ins bit of the ioproc_disable register be set low. note 1: for the purpose of determining the line and pixel position for insertion, the GS9062 will differentiate between psf and interlaced formats by interrogating bits 14 and 15 of the video_format_a register. the packets will be inserted immediately after the eav word. note 2: it is the responsib ility of the user to ensure that there is sufficient space in the horizontal blanking interval for the insertion of the smpte 352m packets. if there are other ancillary data packets present, the smpte 352m packet will be inserted in the first available location in the horizontal ancillary space. ancillary data must be adjacent to the eav. 3.6.3.2 illegal code remapping if the illegal_remap bit of the ioproc_disable register is set low, the GS9062 will remap all codes within the active picture between the values of 3fch and 3ffh to 3fbh. all codes within the activ e picture area between the values of 000h and 003h will be remapped to 004h. in addition, 8-bit trs and ancillary data preambles will be remapped to 10-bit values if this feature is enabled. table 6 host interface description for smpt e 352m packet line number insertion registers register name bit name description r/w default line_352m_f1 address: 1bh 15-11 not used 10-0 line_0_352m[10:0] line number where smpte352m packet is inserted in field 1. this line number overrides the standard line number. if set to zero, the standard line number is used. r/w 0 line_352m_f2 address: 1ch 15-11 not used 10-0 line_1_352m[10:0] line number where smpte352m packet is inserted in field 2. this line number overrides the standard line number. if set to zero, the standard line number is used. r/w 0 table 7 host interface description for smpte 352m payload identifier registers register name bit name description r/w default video_format_b address: 0bh 15-8 smpte352m byte 4 smpte 352m byte 4 information must be programmed in this register when 352m_ins = low. r/w 0 7-0 smpte352m byte 3 smpte 352m byte 3 information must be programmed in this register when 352m_ins = low. r/w 0 video_format_a address: 0ah 15-8 smpte352m byte 2 smpte 352m byte 2 information must be programmed in this register when 352m_ins = low. r/w 0 7-0 smpte 352m byte 1 smpte 352m byte 1 information must be programmed in this register when 352m_ins = low. r/w 0
gennum corporation 22209 - 0 25 of 34 GS9062 3.6.3.3 edh generation and insertion the GS9062 will generate and insert complete edh packets into the data st ream. packet generation and insertion will only take place if the edh_crc_ins bit of the ioproc_disable register is set low. the GS9062 will generate all of the required edh packet data including all ancillary data preambles, (did, dbn, dc), reserved code words and checksum. calculation of both full field (ff) and active picture (ap) crc's will be carried out by the device. smpte rp165 specifies the ca lculation ranges and scope of edh data for standard 525 and 625 component digital interfaces. the GS9062 will util ize these standard ranges by default. if the received video format d oes not correspond to 525 or 625 digital component video standards as determined by the flywheel pixel and line counters, then one of two schemes for determining the edh calculation ranges will be employed: 1. ranges will be based on the line and pixel ranges programmed by the host interface; or 2. in the absence of user-programmed calculation ranges, ranges will be determined from the received trs id words or supplied h, v, and f timing signals (see section 3.3.1). the registers available to the host interface for programming edh calculation ranges include active picture and full field line start and end positions for both fields. table 8 shows the relevant regi sters, which default to '0' after device reset. if any or all of these register values are zero, then the edh crc calculation ranges will be determined from the flywheel generated h signal. the first active and full field pixel will always be the first pixel after the sav trs code word. the last active and full field pixel will always be the last pixel before the start of the eav trs code words. edh error flags (edh, eda, idh, ida and ues) for ancillary data, full field and active picture will also be inserted. these flags must be programmed into the edh_flag registers of the device by the application layer (table 9). note 1: it is the responsibility of the user to ensure that the edh flag registers are updated once per field. the prepared edh packet will be inserted at the appropriate line of the vide o stream according to rp165. the start pixel position of the inserted packet will be based on the sav position of that line such that the last byte of the edh packet (the checksum) will be placed in the sample immediately preceding the start of the sav trs word. note 2: it is also the responsibility of the user to ensure that there is sufficient space in the horizontal blanking interval for the edh packet to be inserted.
gennum corporation 22209 - 0 26 of 34 GS9062 table 8 host interface description for edh calculation range registers register name bit name description r/w default ap_line_start_f0 address: 12h 15-10 not used 9-0 ap_line_start_f0[9:0] field 0 active picture start line data used to set edh calculation range outside of rp 165 values. r/w 0 ap_line_end_f0 address: 13h 15-10 not used 9-0 ap_line_end_f0[9:0] field 0 active picture end line data used to set edh calculation range outside of rp 165 values. r/w 0 ap_line_start_f1 address: 14h 15-10 not used 9-0 ap_line_start_f1[9:0] field 1 active picture start line data used to set edh calculation range outside of rp 165 values. r/w 0 ap_line_end_f1 address: 15h 15-10 not used 9-0 ap_line_end_f1[9:0] field 1 active picture end line data used to set edh calculation range outside of rp 165 values. r/w 0 ff_line_start_f0 address: 16h 15-10 not used 9-0 ff_line_start_f0[9:0] field 0 full field start line data used to set edh calculation range outside of rp 165 values. r/w 0 ff_line_end_f0 address: 17h 15-10 not used 9-0 ff_line_end_f0[9:0] field 0 full fiel d end line data used to set edh calculation range outside of rp 165 values. r/w 0 ff_line_start_f1 address: 18h 15-10 not used 9-0 ff_line_start_f1[9:0] field 1 full field start line data used to set edh calculation range outside of rp-165 values. r/w 0 ff_line_end_f1 address: 19h 15-10 not used 9-0 ff_line_end_f1[9:0] field 1 full fiel d end line data used to set edh calculation range outside of rp-165 values. r/w 0
gennum corporation 22209 - 0 27 of 34 GS9062 table 9 host interface description for edh flag register register name bit name description r/w default edh_flag address: 02h 15 not used 14 anc-ues ancillary unknown error status flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 13 anc-ida ancillary internal device error detected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 12 anc-idh ancillary internal device error detected here flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 11 anc-eda ancillary error detected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 10 anc-edh ancillary error detected here flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 9 ff-ues full field unknown error flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 8 ff-ida full field internal device error detected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 7 ff-idh full field internal device erro r detected flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 6 ff-eda full field error detected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 5 ff-edh full field error detected here flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 4 ap-ues active picture unknown error st atus flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 3 ap-ida active picture internal device error detected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 2 ap-idh active picture internal device error detected here flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 1 ap-eda active picture error detected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0 0 ap-edh active picture error detected here flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. r/w 0
gennum corporation 22209 - 0 28 of 34 GS9062 3.6.3.4 ancillary data checksum generation and insertion the GS9062 will calculate checksums for all detected ancillary data packets presented to the device. these calculated checksum values are inserted into the data stream prior to serialization. ancillary data checksum generation and insertion will only take place if the anc_csum_ins bit of the ioproc_disable register is set low. 3.6.3.5 trs generation and insertion the GS9062 can generate and insert 10-bit trs code words into the data stream as required. this feature is enabled by setting the trs_ins bit of the ioproc_disable register low. trs word generation will be performed in accordance with the timing parameters generat ed by the flywheel which will be locked either to the received trs id words or the supplied h, v, and f timing signals (see section 3.3.1). 3.7 parallel-to-serial conversion the parallel data output of the internal data processing blocks is fed to the parallel-to-serial converter. the function of this block is to generate a serial data stream from the 10- bit or 20-bit parallel data words and pass the stream to the integrated cable driver. 3.8 serial digital data pll to obtain a clean clock signal for serialization and transmission, the input pclk is locked to an external reference signal via the gs906 2's integrated phase-locked loop. this pll is also responsible for generating all internal clock signals required by the device. internal division ratios for the locked pclk are determined by the setting of the 20bit/10bit pin as shown in table 10. 3.8.1 external vco the GS9062 requires the go1525 external voltage controlled oscillator as part of its internal pll. power for the external vco is generated entirely by the GS9062 from an integrated voltage regulator. the internal regulator uses +3.3v supplied on the cp_vdd / cp_gnd pins to provide +2.5v on the vco_vcc / vco_gnd pins. the external vco produces a reference signal for the pll, input on the vco pin of the device. both reference and control signals should be referenced to the supplied vco_gnd as shown in the recommended application circuit of section 4.1. 3.8.2 lock detect output the lock detect block controls the serial digital output signal and indicates to the application layer the lock status of the device via the locked output pin. locked will be asserted high if and only if the internal data pll has locked the pclk signal to the external vco reference signal and one of the following is true: 1. the device is set to operate in smpte mode and has detected smpte trs words in the serial stream; or 2. the device is set to operate in dvb-asi mode and has detected k28.5 sync characters in the serial stream; or 3. the device is set to operate in data-through mode. 3.9 serial digital output the GS9062 contains an integrated current mode differential serial digital cable driver. to enable this output, sdo_en/dis must be set high by the application layer. setting the sdo_en/dis signal low will cause the sdo and sdo output pins to become high impedance, resulting in reduced device power consumption. with suitable external return loss matching circuitry, the GS9062's serial digital outputs will provide a minimum output return loss of -15db at 270mb/s. the integrated cable driver uses a separate power supply of +1.8v dc supplied via the cd_vdd and cd_gnd pins. table 10 serial digital output rates 20 bit /10 bit supplied pclk rate serial digital output rate high 13.5mhz 270mb/s low 27mhz 270mb/s
gennum corporation 22209 - 0 29 of 34 GS9062 3.9.1 output swing nominally, the voltage swing of the serial digital output is 800mvp-p single-ended into a 75 ? load. this is set externally by connecting the rset pin to cd_vdd through 281 ? . the output swing may be decreased by increasing the value of the rset resistor. the relationship is approximated by the curve shown in figure 10. alternatively, the serial digital output swing can drive 800mvp-p into a 50 ? load. since the output swing is reduced by a factor of appr oximately one third when the smaller load is used, the rs et resistor must be 187 ? to obtain 800mvp-p. figure 10 serial digital output swing 3.9.2 serial digital output mute the GS9062 will automatically mute the serial digital output when the locked output signal is low. in this case, the sdo and sdo signals are set to a constant voltage level. 3.10 gspi host interface the gspi, or gennum serial peripheral interface, is a 4-wire interface provided to allow the host to enable additional features of the device and /o r to provide additional status information through configurat ion registers in the GS9062. the gspi comprises a serial data input signal sdin, serial data output signal sdout, an active low chip select cs , and a burst clock sclk. because these pins are shared with the jtag interface port, an additional control signal pin jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals are provided by the host interface. the sdout pin is a high-impedance output allowing multiple devices to be connected in parallel and selected via the cs input. the interface is illustrated in the figure 11 below. all read or write access to the GS9062 is initiated and terminated by the host processor. each access always begins with a 16-bit command word on sdin indicating the address of the register of in terest. this is followed by a 16- bit data word on sdin in write mode, or a 16-bit data word on sdout in read mode. figure 11 gennum serial peripheral interface (gspi) 3.10.1 command word description the command word is transmitted msb first and contains a read/write bit, nine reserv ed bits and a 6-bit register address. set r/w = '1' to read and r/w = '0' to write from the gspi. command words are clocked into the GS9062 on the rising edge of the serial clock sclk. the appropriate chip select signal, cs , must be asserted low a minimum of 1.5ns (t0 in figure 14 and figure 15) before the first clock edge to ensure proper operation. each command word must be followed by only one data word to ensure proper operation. figure 12 command word figure 13 data word 50 ? load 300 400 500 600 700 800 900 1000 250 300 350 400 450 500 550 600 650 700 rset( ? ) ? vsdo(mvp-p) 200 75 ? load sclk cs sdout sdin sclk cs sdin sdout application host GS9062 r/w rsv rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv msb lsb d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 msb lsb
gennum corporation 22209 - 0 30 of 34 GS9062 3.10.2 data read and write timing read and write mode timing for the gspi interface is shown in figure 14 and figure 15 respectively. the maximum sclk frequency allowed is 6.6mhz. when writing to the registers via the gspi, the msb of the data word may be presented to sdin immediately following the falling edge of the lsb of the command word. all sdin data is sampled on the rising edge of sclk. when reading from the regist ers via the gspi, the msb of the data word will be available on sdout 12ns (t 5 in figure 14) following the falling edge of the lsb of the command word, and thus may be read by the host on the very next rising edge of the clock. the remaining bits are clocked out by the GS9062 on the negative edges of sclk. figure 14 gspi read mode timing figure 15 gspi write mode timing 3.10.3 configuration and status registers table 11 summarizes the gs 9062's internal status and configuration registers. all of these registers are available to the host via the gspi and are all individually addressable. where status registers contain less than the full 16 bits of information however, two or more registers may be combined at a single logical address. sdout r/w rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 sclk cs sdin rsv t 0 t 2 t 3 input data setup time duty cycle t 4 period t 5 t 6 output data hold time r/w rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 sclk cs sdin rsv t 0 t 2 t 3 input data setup time duty cycle t 4 period table 11 GS9062 internal registers address register name see section 00h ioproc_disable section 3.6.3 02h edh_flag section 3.6.3.3 04h video_standard section 3.6.2 0ah - 0bh video_format section 3.6.3.1 0eh - 11h raster_structure section 3.6.2 12h - 19h edh_calc_ranges section 3.6.3.3 1bh - 1ch line_352m section 3.6.3.1
gennum corporation 22209 - 0 31 of 34 GS9062 3.11 jtag when the jtag/host input pin of the GS9062 is set high, the host interface port will be configured for jtag test operation. in this mode, pins 27 through 30 become tms, tdo, tdi, and tck. in addition, the reset_trst pin will operate as the test reset pin. boundary scan testing using the jtag interface will be enabled in this mode. there are two methods in which jtag can be used on the GS9062: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly; or 2. under control of the host for applications such as system power on self tests. when the jtag tests are applied by ate, care must be taken to disable any other devices driving the digital i/o pins. if the tests are to be applied only at ate, this can be accomplished with tri-state buff ers used in conjunction with the jtag/host input signal. this is shown in figure 16. figure 16 in-circuit jtag alternatively, if the test capab ilities are to be used in the system, the host may still cntrol the jtag/host input signal, but some means for tri-stating the host must exist in order to use the interface at ate. this is represented in figure 17. figure 17 system jtag please contact your gennum representative to obtain the bsdl model for the GS9062. 3.12 device power up because the GS9062 is designed to operate in a multi-volt environment, any power up sequence is allowed. the charge pump, phase detector, core logic, serial digital output buffers and digital i/o buffers should all be powered up within 1ms of one another. device pins may also be driven prior to power up without causing damage. to ensure that all internal registers are cleared upon power- up, the application layer must hold the reset_trst signal low for a minimum of 1ms after the core power supply has reached the minimum level specified in the dc electrical characteristics table. see s ection 2.2. see figure 18. 3.13 device reset in order to initialize all internal operating conditions to their default states the application layer must hold the reset_trst signal low for a minimum of t reset = 1ms. when held in reset, all device outputs will be driven to a high-impedance state. figure 18 reset pulse application host GS9062 cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe application host GS9062 cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe tri-state core_vdd reset_trst t reset +1.65v +1.8v reset reset t reset
gennum corporation 22209 - 0 32 of 34 GS9062 4. application reference design 4.1 typical application circuit lock 20bit/10bitb ioproc_en/disb data0 data7 data12 data1 data8 data13 data14 data16 data3 data6 data2 data11 data4 data17 data10 data15 data18 data9 data5 detect_trs sdo_en/disb jtag/hostb data19 ioproc_en/disb 20bit/10bitb +1.8v +3.3v +1.8v_a +1.8v +3.3v +3.3v vco_vcc +1.8v_a +1.8v_a +3.3v vco_vcc +1.8v_a GS9062 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 55 54 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 cp_vdd pd_gnd pd_vdd nc dvb_asi 20bit/10bit ioproc_en/dis smpte_bypass rset cd_vdd sdo_en/dis cd_gnd sdo sdo reset_trst jtag/host cs_tms sdout_tdo sdin_tdi sclk_tck nc blank core_gnd f v h core_vdd din0 din1 io_gnd io_vdd din2 dout3 din4 din5 din6 din7 din8 io_gnd din9 din10 din11 io_vdd din13 din12 din14 din15 din16 din17 io_gnd io_vdd din18 din19 core_vdd nc nc detect_trs core_gnd pclk locked vco vco vco_gnd vco_vcc lf cp_cap lb_cont cp_gnd 75 go1525 5 4 8 2 7 1 3 6 vctr gnd gnd gnd vcc o/p nc gnd 10n l 75 281 +/-1% 1u 1u c 0 bnc 10n 10n r l c55 10n r c 100n 10 n 10n bnc 10n 4u7 10n 10n 0 15k 1u 1 2 1u 4u 7 2n2 1u 10n 10n 75 10n 0 10n 1u 10n f v h pclk data[19..0] dvb_asi reset_trstb lock blankb smpte_bypassb sclk_tck sdout_tdo sdin_tdi csb_tms jtag/hostb detect_trs sdo_en/disb 20bit/10bitb ioproc_en/disb r, l, c form the output return loss compensation network. values are subject to change. jtag/hostb detect_trs sdo_en/disb smpte_bypassb dvb_asi pclk blankb lock blankb dvb_asi smpte_bypassb gnd_a gnd_a gnd_a gnd_a gnd_a gnd_d gnd_d gnd_d gnd_d gnd_a gnd_d gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco rsv nc nc nc nc nc nc nc nc nc nc vco_vcc gnd_a nc
gennum corporation 22209 - 0 33 of 34 GS9062 5. references & relevant standards smpte 125m component video signal 4:2:2 ? bit parallel interface smpte 291m ancillary data packet and space formatting smpte 293m 720 x 483 active line at 59.94 hz prog ressive scan production ? digital representation smpte 352m video payload identificati on for digital television interfaces smpte rp165 error detection checkwords and status flags for use in bit-serial digital interfaces for television smpte rp168 definition of vertical interval s witching point for synchronous video switching 6. package & ordering information 6.1 package dimensions tolerances of form and position symbol min nom max min nom max millimeter inch 80l b e aaa ccc bbb d2 e2 0.22 0.65 bsc 0.026 bsc 12.35 0.20 0.20 0.10 0.008 0.008 0.004 0.486 0.486 12.35 0.30 0.38 0.009 0.012 0.015 notes: diagram shown is representative only. table x is fixed for all pin sizes, and table y is specific to the 80-pin package. table y ddd 0.13 0.005 table x control dimensions are in millimeters. 1. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 2. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages.
22209 - 0 34 of 34 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nishi shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that the y are free from patent infringement. ? copyright may 2002 gennum corporation. all rights reserved. printed in canada. caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation GS9062 document identification preliminary data sheet the product is in a preproduction phase and specifications are subject to change without notice. 6.2 ordering information part number package temperature range GS9062-cf 80-pin lqfp 0c to 70c 7. revision history version ecr date changes and/or modifications a 120604 july 2002 new document. b 126380 september 2002 update ac/dc parameters. correct pin descriptions. add reflow profile. insert i/o diagrams. add jtag information. 0 130132 july 2003 upgrade to preliminary data sheet. reformat detailed description and expand information. ac/dc parameters updated. reset operation clarified. edit pin descriptions. correct register addresses.

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